FIG. 1 illustrates a block diagram of a parser 100. As shown in FIG. 1, the parser 100 includes N parser engines 105 placed in series. The N parser engines 105 placed in series allows the parser 100 to parse at a high line rate. A network packet entering the parser 100 is processed by each of the N parser engines 105. Each parser engine 105 has some latency through it. Thus, if each parser engine 105 has a latency of T cycles, there is the total latency N*T clocks through the parser 100. Each network packet that goes through the parser 100 will incur this fixed latency. However, in networking, not all packets require all the processing that is provided by the multiple parser engines 105.